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g = 0.2, level translation, 16 - bit adc driver ad8275 rev. a information furnished by analog devices is believed to b e accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.47 00 www.analog.com fax: 781.461.3113 ? 2008 - 2010 analog devices, inc. all rights reserved. features translates 10 v to +4 v drives 16 - bit sar adcs small msop p ackage input overvoltage: +40 v to ?35 v ( v s = 5 v) fast settling t ime : 4 5 0 ns to 0.001% rail - to - rail o utput wide supply o peration: +3.3 v to + 15 v high cmrr : 80 db low g ain drift : 1 ppm/ c low o ffset d rift : 2.5 v/c applications level translator adc d river instrumen tation amplifier building block automated test equipment pin c onfiguration 07546-001 ref1 1 ?in 2 +in 3 ?v s 4 ref2 8 +v s 7 out 6 sense 5 ad8275 top view (not to scale) figure 1. typical application 07546-002 vref 4.096v ad8275 7 4 5 6 8 2 50k? 0.1f 50k? 20k? 20k? 33? 10k? 3 +in ?in vin ref2 ref1 ?v s +v s +5v out sense 0.1f 2.7nf 10f 1 ad7685 vdd gnd ref in+ in? + 10 v ?10 v +4. 048 v +0. 048 v +2. 048 v figure 2. tran slating 10 v to 4.096 v adc full s cale general description the ad8275 is a g = 0.2 difference amplifier that can be used to translate 10 v signals to a +4 v level. it solves the problem typically encountered in industrial and instrumentation applic - ati ons where 10 v signals must be interfaced to a single - supply 4 v or 5 v adc. the ad8275 interfaces the two signal levels, simplifying design. the ad 8275 has fast settling time of 4 5 0 ns and low distortion, making it suitable for driving medium speed succe ssive approx - imation (sar) adcs. its wide input voltage range and rail - to - rail outputs make it an easy to use building block. single - supply operation reduces the power consumption of the amplifier and helps to protect the adc from overdrive conditions. int ernal, matched, precision laser - trimmed resistors ensure low gain error, low gain drift of 1 ppm/c (max imum ) , and high common - mode rejection of 80 db. low offset and low offset drift, combined with its fast settling time, make the ad8275 suitable for a v ariety of data acquisition applications where accurate and quick capture is required. the ad8275 can be used as an analog front end , or it can follow buffers to level translate high voltages to a voltage range accepted by the adc. in addition, the ad8275 can be configured for diff - erential outputs i f used with a differential adc. the ad8275 is available in a space - saving, 8 - lead msop and is specified for performance over the ?40c to +85c temperature range. table 1 . difference amplifiers by category low distortion high voltage single - supply current sense ad8270 ad628 ad8202 ad827 3 ad629 ad8203 ad827 4 ad8205 ad8275 ad8206 AMP03 ad8216
ad8275 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuration ............................................................................. 1 typical application ........................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 maximum power dissipation ..................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 11 bas ic connection ........................................................................ 11 power supplies ............................................................................ 12 reference ..................................................................................... 12 common - mode inpu t voltage range ..................................... 12 input protection ......................................................................... 12 configurations ............................................................................ 13 applica tions information .............................................................. 14 driving a single - ended adc ................................................... 14 differential outputs ................................................................... 14 increasing input impedance ..................................................... 15 ac coupling ............................................................................... 15 using the ad8275 as a level translator in a data acquisition system .......................................................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 8/10 rev. 0 to rev. a changes to figu re 40 ...................................................................... 14 10 /0 8 revision 0: initial version
ad8275 rev. a | page 3 of 16 specifications v s = 5 v, g = 0.2, ref1 connected to gnd and ref2 connected to 5 v , r l = 2 k ? connected to v s /2 , t a = 25c, unless otherwise noted. specifications referred to output unless otherwise noted. table 2 . a grade b grade parameter test conditions /comments min typ max min typ max unit dynamic performance small signal bandwidth ?3 db 10 15 10 15 mhz slew rate 4 v step 20 25 20 25 v/s settling time to 0.01% 4 v step on output, c l = 100 pf 350 350 450 ns settling time to 0.001% 4 v step on output, c l = 100 pf 450 450 550 ns overload recovery time 50% o verdrive 300 300 ns noise/distortion 1 thd + n f = 1 khz, v out = 4 v p - p, 22 khz band pass fi lter 106 106 db voltage noise f = 0.1 hz to 10 hz , referred to output 1 4 1 4 v p-p spectral noise density f = 1 khz , referred to output 40 40 nv/ hz gain v ref2 = 4.096 v, ref1 and r l connected to gnd , (v in+ ) ? (v in ? ) = ?10 v to +10 v 0.2 0.2 v/v gain error 0.024 0.024 % gain drift ?40c to +85c 1 3 0.3 1 ppm/c gain nonlinearity v out = 4 v p - p, r l = 600 ?, 2 k?, 10 k? 2.5 2.5 3 ppm offset and cmrr offset 2 referred to output, v s = 2.5 v, reference and input pins grounded 300 700 150 500 v vs. temperature ?40c to +85c 2.5 2.5 7 v/c vs. power supply v s = 3.3 v to 5 v 90 100 db reference divider accuracy 0.024 0.024 % common - mode rejection ratio 3 v cm = 10 v , referred to output 80 96 86 db input characteristics input voltage range 4 ?12.3 + 12 ?12.3 + 12 v impedance 5 differential v cm = v s /2 108||2 108||2 k?||pf common mod e 27.5||2 27.5||2 k?||pf output characteristics output swing v ref2 = 4.096 v, ref1 and r l connected to gnd, r l = 2 k ? ?v s + 0.048 +v s ? 0.1 ?v s + 0.048 +v s ? 0.1 v capacitive load 6 100 100 pf short- circuit current limit 30 30 ma power supply specified voltage range 5 5 v operating voltage range 3.3 15 3.3 15 v supply current i o = 0 ma, v s = 2.5 v, reference and input pins grounded 1.9 2.3 1.9 2.3 ma o ver temperature i o = 0 ma, v s = 2.5 v, reference and i nput pins grounded, ?40c to + 85c 2.1 2.7 2.1 2.7 ma temperature range specified performance ?40 +85 ?40 +85 c 1 includes amplifier voltage and current noise, as well as noise of internal resistors. 2 includes input bias and offset current errors. 3 see figure 7 for cmrr vs. temperature. 4 the input voltage range is a function of the voltage supplies, reference voltage, and esd diodes. when operating on other sup pl y voltages, see the absolute maximum ratings section, figure 11 , and table 5 for more information. 5 internal resistors are trimmed to be ratio matched but have 20% absolute acc uracy. 6 see figure 25 to figure 28 in the typical performance characteristics section for more information.
ad8275 rev. a | page 4 of 16 absolute maximum rat ings table 3 . parameter rating supply voltage 18 v output short - circuit current see derating curv e ( figure 3 ) voltage at +in, ? in pins ?v s + 40 v, +v s ? 40 v voltage at refx, +v s , ? v s , sense, and out pin s ?v s ? 0. 5 v, +v s + 0. 5 v current into refx, +in, ?in , sense, and out pin s 3 ma storage temperature range ?65c to +13 0c specified temperature range ?40c to +85c thermal resistance ( ja ) 13 5c/w package glass transition temperature (t g ) 140c esd human body model 2 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the devi ce. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissip ation the maximum safe power dissipation in the ad8275 package is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die locally reaches the junction te mperature. at approximately 140c, which is the glass transition temperature, the plastic changes its prope rties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, perm a nently shifting the paramet ric performance of the ad8275 . exceeding a junction temperature of 140c for an extended period can result in changes in silicon devices, p o tentially causing failure. the still air thermal properties of the package and pcb ( ja ), the ambient temperature (t a ), and the total power dissipated in the package (p d ) determine the junction temperature of the die. the junction temperature is calculated as follows: t j = t a + ( p d ja ) the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the pac k age due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current ( i s ). assuming the load (r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is dissipated in the package and some of which is diss i pated in the load (v out i out ). the difference between the total drive power and the load p ower is the drive power dissipated in the package. p d = quiescent power + ( total drive power ? load power ) ( ) l out l out s ss d r v r v v ivp 2 C 2 ? ? ? ? ? ? ? ? += in single - supply operation with r l referenced to Cv s , the worst case is v out = v s /2. airflow increases heat dissipation, effe ctively reducing ja . in addition, more metal directly in contact with the package leads from metal traces , through holes, ground, and power planes reduces ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temper ature on a 4 - layer jedec standard board. 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 ?40 0 ?20 20 40 60 80 100 120 07546-003 maximum power dissipation (w) ambient temperature (c) figure 3 . maximum power dissipation vs. ambient temperature esd caution
ad8275 rev. a | page 5 of 16 pin configuration and function descripti ons 07546-001 ref1 1 ?in 2 +in 3 ?v s 4 ref2 8 +v s 7 out 6 sense 5 ad8275 top view (not to scale) figure 4. pin conf iguration table 4 . pin function descriptions pin no. mnemonic description 1 ref1 reference pin. s ets the output voltage level (see the reference section). 2 ? in negative input pin . 3 +in positive input pin . 4 ?v s negative supply pin . 5 sense sense output pin . tie this pin to the out pin. 6 out output pin (force output). 7 +v s positive supply pin . 8 ref2 reference pin. s ets the output voltage level (see t he reference section).
ad8275 rev. a | page 6 of 16 typical performance characteristics v s = 5 v, g = 0.2, ref1 connected to gnd and ref2 connected to 5 v , r l = 2 k ? connected to v s /2 , t a = 25c, unless otherwise noted . 07546-004 offset voltage (v) hits 0 2 4 6 10 8 12 14 ?600 ?400 ?200 0 200 400 600 figure 5 . typical distribution of system offset voltage, referred to output 07546-005 cmrr (v/v) hits 0 10 20 30 40 50 60 70 ?60 ?40 ?20 0 20 40 60 figure 6 . typical distribution of cmrr, referred to output 07546-006 temperature (c) cmrr (v/v) 60 40 20 0 ?20 ?40 ?60 ?40 ?20 0 20 40 60 80 100 120 figure 7 . cmrr vs. temperature, normalized at 25c 07546-007 temperature (c) offset voltage (v) ?40 ?20 0 20 40 60 80 100 120 ?300 ?250 ?200 ?150 ?100 ?50 50 0 100 150 200 250 300 normalized at 25c, representative samples figure 8 . offset voltage vs. temperature, normalized at 25c, referred to output 07546-008 temperature (c) gain error (v/v) ?45 ?30 ?15 0 15 30 45 60 75 90 105 120 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 gain error normalized at 25c figure 9 . gain error vs. temperature, normalized at 25c 07546-009 temperature (c) ?50 ?25 5 4 3 2 1 0 quiescent current (ma) 25 50 75 3.3v 100 125 5v figure 10 . quiescent current vs. temperature
ad8275 rev. a | page 7 of 16 07546-010 output voltage (v) input common-mode voltage (v) ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5. 0 5.5 35 30 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 figure 11 . input common - mode voltage vs. output voltage, no load 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 gain (db) 1k 100 10k 100k 1m 100m 10m 07546-011 frequency (hz) figure 12 . gain vs. frequency 07546-012 40 50 60 80 70 90 100 100 1k 10k 100k 10m 1m frequency (hz) common-mode rejection (db) figure 13 . common - mode rejection vs. frequency, referred to in put 07546-013 frequency (hz) power supply rejection (db) ?20 0 20 40 60 80 100 120 100 1m 100k 10k 1k fi gure 14 . power supply rejection vs. frequency, referred to output 07546-014 6 5 4 3 2 1 0 maximum output voltage (v p-p) 1k 100 10k 100k 1m 10m frequency (hz) figure 15 . maximum output voltage vs. frequency 07546-015 20 15 10 5 ?5 ?15 0 ?10 ?20 0 1 2 3 4 gain nonlinearity (ppm) output voltage (v) figure 16 . gain nonlinearity, r l = 600 , 2 k , 10 k
ad8275 rev. a | page 8 of 16 07546-016 60 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?25 ?50 0 25 50 75 100 125 current (ma) temperature (c) 5v sink 3.3v sink 5v source 3.3v source figure 17 . short - circuit current vs. temperature, v s = 3.3 v , 5 v 07546-017 +v s +v s ? 0.2 +v s ? 0.4 +v s ? 0.6 +v s ? 0.8 +v s ? 1.0 ?v s + 1.0 ?v s + 0.8 ?v s + 0.6 ?v s + 0.4 ?v s + 0.2 ?v s output voltage swing (v) (referred to supply rails) 1k 10k 100 100k r load (?) ? 40c ?40c +125c +25c +85c +125c +25c +85c figure 18 . output voltage swing vs. r load , v s = 5 v +v s +v s ? 0.4 +v s ? 0.8 +v s ? 1.2 +v s ? 1.6 +v s ? 2.0 ?v s + 2.0 ?v s + 1.6 ?v s + 1.2 ?v s + 0.8 ?v s + 0.4 ?v s output voltage swing (v) (referred to supply rails) 2 4 6 8 10 12 14 0 output current (ma) ? 40c +125c +25c +125c 07546-018 +85c +25c +85c ?40c figure 19 . output voltage swing vs . output current , v s = 3.3 v +v s +v s ? 0.4 +v s ? 0.8 +v s ? 1.2 +v s ? 1.6 +v s ? 2.0 ?v s + 2.0 ?v s + 1.6 ?v s + 1.2 ?v s + 0.8 ?v s + 0.4 ?v s output voltage swing (v) (referred to supply rails) 2 4 6 8 10 12 14 0 output current (ma) ? 40c 07546-119 ?40c +125c +85c +25c +125c +85c +25c figure 20 . output voltage swing vs. output current , v s = 5 v 07546-019 frequency (hz) voltage noise density (nv/ hz) 10 100 1k 1 10 100 1k 10k 100k figure 21 . voltage noise density vs. frequency, referred to output 07546-020 time (1s/div) voltage noise (1v/div) figure 22 . 0.1 hz to 10 hz voltage noise, r eferred to output
ad8275 rev. a | page 9 of 16 07546-021 40 35 30 25 20 15 10 5 0 ?40 ?20 0 20 40 60 80 100 120 slew rate (v/s) temperature (c) +sr ?sr figure 23 . slew rate vs. temperature 07546-022 1s/div 20mv/div c load = 47pf 600? 2k? 10k? no load figure 24 . small signal step response for various resistive loads (step responses staggered for clarity) 07546-023 1s/div 20mv/div no resistive load 20pf 47pf no cap 100pf figure 25 . small signal pulse response for various capacitive loads (step responses staggered for clarity) 07546-024 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 capacitance (pf) overshoot (%) 3.3v 5v figure 26 . small signal overshoot vs. capacitive load, no resistive load 07546-025 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 capacitance (pf) overshoot (%) 3.3v 5v fig ure 27 . small signal overshoot vs. capacitive load, 600 in p arallel with capacitive load 07546-026 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 capacitance (pf) overshoot (%) 3.3v 5v figure 28 . small signal overshoot vs. capacitive load, 2 k in p arallel with capacitive load
ad8275 rev. a | page 10 of 16 07546-027 10v/div 2s/div 10mv/div figure 29 . large s ignal pulse response and settling time, r l = 2 k 07546-029 1.0 0.1 0.01 0.001 0.0001 10 100 10k 1k 100k thd + n (%) frequency (hz) r l = 600 r l = 10k r l = 2k v out = 4v p-p figure 30 . thd + n vs. frequency, v out = 4 v p -p
ad8275 rev. a | page 11 of 16 theory of operation the ad8275 level translates 10 v signals at its inputs to 4 v at its output. it does this by atte nuating the input signal by 5. a subtractor network performs the attenuation, the level shifting, and the differential - to -single- ended conversion. one benefit of the subtractor topology is that it can accept input signals beyond its supply voltage. the su btractor is composed of tightly matched resistors. by integrating the resistors and trimming the resistor ratios, the ad8275 achieves 80 db cm r r and 0.024 % gain error. 07546-030 input esd ref2 +v s +v s +v s ?v s ?v s +v s ?v s ?v s +v s ?v s ?v s out sense 50k? 7k? 7k? 50k? 20k? 20k? 10k? 2.5v ?in +in input esd +v s ?v s ref1 +v s ?v s figure 31 . ad8275 simplified schematic to achieve a wider in put voltage range, the ad8275 uses an internal 2.5 v voltage bias tied to Cv s and two 7 k resistors , as shown in figure 31 . the resistors help to set the common mode of the internal amplifier. the benefit of this circuit is that it extends the input range without causing crossover distortion typical of amplifiers that have rail - to - rail complementary transistor inputs. the input range of the internal op amp is +v s ? 0.9 v to ?v s + 1. 3 5 v. ?10 ?8 ?6 600 400 200 0 ?200 ?400 ?600 ?4 ?2 0 2 4 6 8 10 common-mode voltage (v) offset (v) 07546-132 figure 32 . a d 82 75 does not have crossover distortion typical of rail -to- rail input amplifiers the ad8275 employs a balanced, high gain, linear output stage that adaptively generates current as required , eliminating the dynamic errors found in other amplifiers. this is u seful when driving sar adcs , which can deliver kickback current into the output of the amplifier. the result is a design that achieves low distortion, consistent bandwidth , and high slew r ate. basic connection the basic configurations for the ad8275 are s hown in figure 33 and figure 34 . in figure 33 , ref1 and ref2 are tied together. a voltage, v ref , applied to the tied ref 1 and re f2 pins , set s the output voltage level to v ref . for example , in figure 33 , if v ref = 2 v and the inputs are tied to ground, the output remains at 2 v. 07546-031 ad8275 7 4 5 6 8 1 2 50k? 0.1f 50k? 20k? 20k? 10k? 3 v inn +in ?in v inp ref2 v ref v out ref1 ?v s +v s +5 v out sense v out = + v ref (v inp ) ? (v inn ) 5 figure 33 . basic con figuration 1 : s hared reference in contrast, figure 34 shows ref1 tied to ground and ref2 tied to v ref . in this example, the two 20 k resistors serve as a resistor divider , and v ref is divided by 2 . for example, if both inputs o f the ad8275 are grounded and v ref = 5 v , the output is 2.5 v. 07546-032 ad8275 7 4 5 6 8 1 2 50k? 0.1f 50k? 20k? 20k? 10k? 3 v inn +in ?in v in p ref2 v ref v out ref1 ?v s +v s +5v out sense v out = + (v inp ) ? (v inn ) 5 v ref + 0v 2 figure 34 . basic con figuration 2 : split reference
ad8275 rev. a | page 12 of 16 power supplies use a stable dc voltage to power the ad8275. noise on the supply pins can adversely affect performan ce. place a bypass capacitor of 0.1 f between each supply pin and ground, as close to each pin as possible. a tantalum capacitor of 10 f should also be used between each supply and ground. it can be farther away from the ad8275 and typically can be shar ed by other precision integrated circuits. reference the reference terminals are used to provide a bias level for the output. for example, in a single - supply 5 v operation, the reference terminals can be set so that the output is biased at 2.5 v . this ens ures that the output can swing positive or negative around a 2.5 v level. figure 33 and figure 34 illustrate two different ways to set the reference voltage. see the basic connection section for the differ ences between the two settings. the allowable reference voltage range is a fu nction of the common - mode input and supply voltages. the ref 1 and ref2 pin s should not exceed either +v s or ?v s by more than 0.5 v. t he ref x terminal s should be driven by low source impedance because parasitic resistance in series with ref1 and ref2 can adversely affect cmrr and ga in accuracy. 20k? 20k? ref2 ref1 50k? ?in incorrect correct 07546-033 7 4 5 6 8 1 2 50k? 50k? 20k? 20k? 10k? 3 ?in +in ref2 v ref ref1 ?v s +v s out sense 3 ad8275 7 4 5 6 8 2 50k? 10k? 3 +in v ref ?v s +v s out sense ad8275 1 20k? 20k? ref2 ref1 50k? ?in 7 4 5 6 8 1 2 50k? 50k? 20k? 20k? 10k? 3 ?in +in ref2 v ref ref1 ?v s +v s out sense ad8275 4 5 6 8 2 50k? 10k? 3 +in v ref ?v s +v s out sense ad8275 1 in 2 50 0k? r ref1 1 0k? 5 +in nse in 2 50 0k? r ref1 1 0k? 5 +in o nse 7 figure 35 . ref 1 and ref2 pin guidelin es common-mode input voltage range the common - mode voltage range is a function of the input voltage range of the internal op amp, the supply voltage, and the reference voltage. equation 1 expresses the maximum positive c ommon - mode voltage range . v cm_pos 13.14(+v s ) C 7.14( Cv s ) C 5(( ref1 + ref2 )/2) C 29.69 (1) equation 2 expresses the minimum c ommon - mode voltage range. v cm_neg 6( Cv s ) C 5(( ref1 + ref2 )/2) C 0.11 (2) the voltage range of the internal op amp varies depending on temperature. the equations reflect a typical input voltage range of +v s ? 0.9 v and ?v s + 1.35 v over temperature. table 5 lists expected common - mode ranges for typical configurations . table 5 . expected c ommon -m ode voltage range for t ypical configurations +v s (v) 1 v ref1 (v) v ref2 (v) v cm + (v) v cm ? (v) 5 5 0 23.5 ?12.6 5 2.5 0 29.8 ?6.4 5 4.096 0 25.8 ?10.4 3.3 3.3 0 5.4 ?8.4 3.3 2.5 0 7.4 ?6.4 5 5 5 11.0 ?25.1 5 4.096 4.096 15.5 ?20.6 5 3 3 21.0 ?15.1 5 2.5 2.5 23.5 ?12.6 5 2 .048 2.048 25.8 ?10.4 5 1.25 1.25 29.8 ?6.4 5 0 0 36.0 ?0.1 1 Cv s = 0 v. input protection the inputs of the ad8 2 75, +in and ? in, are protected by esd diodes that clamp 40 v above ?v s and 40 v below + v s . when operating on a single +5 v supply, the esd d iode conducts at input voltages less than ? 35 v and greater than +40 v. if the input voltage is expected to exceed the maximum ratings of the ad8275 , use external transorbs. adding series resistors to the inputs of the ad8275 is not recommended because the internal resistor ratios are matched to provide optimal cm r r and gain accuracy. adding external series resistors to the input degrade s the performance of the ad8275 . all other pins are protected by esd diodes that clamp 0.5 v beyond either supply rail. for example, the voltage range of the ref1 and ref2 pin s on a 5 v supply is ?0.5 v to +5.5 v.
ad8275 rev. a | page 13 of 16 configurations figure 36 and figure 37 , along with table 6 and table 7 , provide examples of the possible input and output ranges for various supplies and reference voltages . note that table 6 and table 7 list the typical voltage range of the ad8275; these values do not reflect variation over process or temperature. hi +swing ?swing useful v out linear v in range lo hi lo mid 07546-136 v ref ad8275 7 4 5 6 8 2 50k? 0.1f 50k? 20k? 20k? 10k? 3 +in ?in v inp v inn ref2 ref1 ?v s +v s +5v out sense 1 v out hi +s wing ?swing useful v out linear v in range lo hi lo mid 07546-137 v ref ad8275 7 4 5 6 8 2 50k? 0.1f 50k? 20k? 20k? 10k? 3 +in ?in ref2 ref1 ?v s +v s +5v out sense 1 v out v inp v inn figure 36 . split reference figure 37 . shared reference table 6 . input and output relationships for split reference configuration in figure 36 +v s 1 v ref v out for v in = 0 v linear differential v in range useful v out ranges 5 v 5 v 2.5 v high: + 12 v mid: 0 v low: ?12.3 v high: + 4.95 v swing: + 2.45 v, ?2.455 v low: + 0.045 v 5 v 2.5 v 1.25 v high: + 18.3 v mid: 0 v low: ?6 v high: + 4.95 v swing: + 3.7 v, ?1.205 v low: + 0. 045 v 5 v 4.096 v 2.048 v high: + 14.3 v mid: 0 v low: ?10 v high: + 4.95 v swing: + 2.902 v, ?2.003 v low: + 0.045 v 3.3 v 3.3 v 1.65 v high: + 8 v mid: 0 v low: ?8 v high: + 3.24 v swing: + 1.59 v, ?1.605 v low: + 0.045 v 3.3 v 2.5 v 1.25 v high: + 10 v mid: 0 v low: ?6 v high: + 3.24 v swing: + 1.99 v, ?1.205 v low: + 0.045 v 1 ?v s = 0 v. table 7 . input and output relationships for shared reference configuration in figure 37 +v s 1 v ref v out for v in = 0 v linear differential v in range useful v out ranges 5 v 5 v 5 v high: ?0.1 v mid: 0 v low: ?24.7 v high: + 4.98 v swing: ?4.94 v low: + 0.06 v 5 v 4.096 v 4.096 v high: + 4.4 v mid: 0 v low: ?20.2 v high: + 4.98 v swing: + 0.884 v to ?4.03 v low: + 0.06 v 5 v 3 v 3 v high: + 9.5 v mid: 0 v low: ?14.8 v high: + 4.95 v swing: + 1.9 v, ?2.955 v low: + 0.045 v 5 v 2.5 v 2.5 v high: + 12 v mid: 0 v low: ?12.3 v high: +4 .95 v swing: + 2.45 v, ?2.455 v low: + 0.045 v 5 v 2.048 v 2.048 v high: + 14.3 v mid: 0 v low: ?10 v high: + 4.9 5 v swing: + 2.902 v, ?2.003 v low: + 0.045 v 5 v 1.25 v 1.25 v + 18.3 v to ? 6 v high: + 4.95 v swing: + 3.7 v, ?1.205 v low: + 0.045 v 0 v 0 v 0 v 24.5 v to 0.2 v high: 4.95 v swing: 4.95 v low: 0.045 v 1 ?v s = 0 v.
ad8275 rev. a | page 14 of 16 applications information driving a si ngle - ended adc the ad8275 provides the common - mode rejection that sar adcs often lack. in addition, it enables designers to use cost - effective, precision, 16 - bit adcs such as the ad7685 , yet still condition 10 v signals. one important factor in selecting an adc driver is its ability to settle within the acquisition window of the adc . the ad8275 is able to drive medium speed sar adcs. in figure 38 , the 2.7 nf capacitor serves to store and deliver necessary charge to the switched cap acitor input of the adc. the 33 series resistor reduces the burden of the 2.7 nf load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the ad7685. t he output impedance of the amplifier can affect the thd of the adc . in this case, the combined impedance of the 33 resistor and the output impedance of the ad8275 provides extremely low thd of ? 112 db. figure 39 shows the ac res ponse of the ad8275 driving the ad7685 . 07546-034 vref (adr444, adr445) ad8275 7 4 5 6 8 2 50k? 0.1f 50k? 20k? 20k? 33? 10k? 3 +in ?in vin ref2 ref1 ?v s +v s +5v out sense 0.1f 2.7nf 10f 1 ad7685 vdd gnd ref in+ in? figure 38 . driving a single - ended adc 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 0 1 4 7 10 07546-139 adc full scale (db) frequency (khz) 2 5 8 3 6 9 figure 39 . fft of ad8275 directly driving the ad7685 us ing the 5 v reference of the e valuation board (i nput = 20 v p- p, 1 khz , thd = ? 112 db ) the ad8275 c an condition signals for hi gher resolution adcs such as 18 - bit sar converters, provided that a narrower bandw idth is sampled to limit noise. differential outputs in certain applications, it is necessary to create a differential signal. for example, h igh resolution adcs often require a differential input. in other cases, transmission over a long distance can require differential signals for better immunity to interference. figure 40 shows how to configure the ad 8275 to output a differential signal. the ad 8655 op amp is used in an inverting topology to create a differential voltage. vref sets the output midpoint. errors from the op amp are common to b oth outputs and ar e thus common mode. likewise, errors from using mismatched resistors cause a common - mode dc offset error. such errors are rejected in differential signal processing by differential input adcs or by instrumentation amplifiers. when using this circuit to dri ve a differential adc, v ref can be set using a resistor divider from the adc reference to make the output ratiometric with the adc. 07546-035 ad8275 7 4 5 6 8 2 50k? 0.1f 0.1f 8.2f 50k? 20k? 20k? 2k? 2k? 10k? 3 +in ?in ref2 ref1 ?v s +v s +5v +10v ?10v +5v out sense 1 ad8655 v ref = 2.5v +v out ?v out +3.5v +1.5v +2.5v +3.5v +1.5v +2.5v figure 40 . ad8275 c onfigured for d ifferential o utput (for d riving a d ifferential adc )
ad8275 rev. a | page 15 of 16 increas ing in put impedance in applications where a high input impedance is needed, low input bias current op amps can be used to buffer the ad8275. in figure 41 , an ad8620 is used to provide high input imped - ance. input bias current is limited to 10 pa. 07546-036 ad8275 7 4 5 6 8 1 2 1 3 2 7 6 5 4 8 50k? 0.1f 50k? 20k? 20k? 10k? 3 ?in 1/2 2/2 +in ref2 v ref ref1 ?v s ?13v 0.1f 0.1f +v s +5v +13v out v out sense inverting input non- inverting input ad8620 ad8620 figure 41 . adding o p a mp b uffers for h igh i nput i mpedance ac coupling an integrator can be tied to the ad8275 in feedback to create a high - pass filter as shown in figure 42 . this circuit can be used to reject dc voltages and offsets. at low frequencies, the impedance of the capacitor, c, is high. thus, the gain of the integrator is high. dc voltage at the output of the ad8275 is inverted and gai ned by the integrator. the inverted signal is injected back into the refx pins, nulling the output. in contrast, at high fre - quencies, the integrator has low gain because the impedance of c is low. voltage changes at high frequencies are inverted but at a low gain. the signal is injected into the ref x pins but it is not enough to null the out put. high frequency signals are, therefore , allowed to pass. when a signal exceeds f high - pass , the ad8275 outputs the condition ed input signal. 07546-037 ad8275 7 4 5 6 8 2 50k? 0.1f 0.1f 50k? 20k? 20k? r c 10k? 3 +in ?in ref2 ref1 v ref ?v s +v s +5v +5v out v out sense v out 1 f high-pass = 1 2 rc op am p figure 42 . ac - coupled level translator using the ad8275 as a l evel t ranslator in a data acquisition system signal size varies dramatically in some data acquisition applica - tions. instrumentation amplifiers, such as the ad8253 , ad8228 , or ad8221 , are often used at the inputs to provide cmr r and high input impedance. however, the inst rumentation amplifiers output 10 v s ignals and the adc full scale is 5 v or 4.096 v. in figure 43 , the ad8275 serves as a level translator between the in - amp and the ad c. the ad8275 , along with the ad8228 and the ad8253 , have very low gain drift because all gain setting resistors are internal and laser - trimmed. 07546-143 vref ad8275 7 4 5 6 8 2 50k? 0.1f 50k? 20k? 20k? 33? 10k? 3 +in ?in ref2 ref1 ?v s +v s +5v out sense 0.1f 2.7nf 10f 1 adc vcc gnd ref +in ?in 0.1f + 15 v ? 15 v 0.1f in-amp figure 43 . level translat ion in a data acquisition system
ad8275 rev. a | page 16 of 16 outline dimensions compliant to jedec standards m o-187-aa 6 0 0.80 0.55 0 .40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2 .80 coplanarity 0.10 0 .23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 44 . 8- lead mini small outline package [ msop] (rm -8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option brand ing ad8275armz ?40c to +85c 8- lead msop rm -8 y13 ad8275armz -r7 ?40c to +85c 8- lead msop , 7 tape and reel rm -8 y13 ad8275armz -rl ?40c to +85c 8- lead msop , 13" tape and reel rm -8 y13 ad8275brmz ?40c to +85c 8- lead msop rm -8 y1v ad8275brmz -r7 ?40c to +85c 8-l ead msop , 7 tape and reel rm -8 y1v ad8275brmz -rl ?40c to +85c 8- lead msop , 13" tape and reel rm -8 y1v 1 z = rohs compliant part. ? 2008 - 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07546 -0- 8/10(a)

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